Silicon Carbide Substrate 3C/6H/ Dummy Grade SiC Wafer in round container with blue-green gel surface.
Silicon Carbide Substrate 3C/6H/ Dummy Grade SiC Wafer, high-quality research SiC wafers.

Silicon Carbide Substrate 3C/6H/ Dummy Grade SiC Wafer

$507.00
Type:3C N Type
Size:10x10mm
Quantity:1 Piece
Quantité:
♦️High-quality SiC wafer for Optical.
♦️Provide thinning process, thickness from 100um.
♦️Global shipping, secure payment, large inventory.
♦️Minimum delivery time within 1 week. Shipped by FedEx, DHL,UPS, etc.
SiC Substrate Specification:
  • Size: 10x10mm;
  • Poly type: 3C;
  • Thickness: 350um±25;
  • Surface Orientation : On axis:(111)±0.5;
  • Micropipe Density: 0 cm-2;
  • Resistivity <1Ω・cm;
  • TTV≤5μm;
  • Warp≤15μm;
  • Bow≤-30μm;
  • Surface Roughness: CMP Ra<0.5 nm;
  • Edge Cracks: 3 allowed, single length≤2 mm;
  • Silicon Surface Scratches : 8 scratches to 1xwafer diametercumulative length;
  • Edge Chips : 5 allowed, <1mm each;
  • Silicon Surface Contamination : None;
  • Edge Exclusion : 6mm;
  • Packing: Multi-wafer Cassette Or Single Wafer Container;
  • Production time: 4~5weeks;
    ♦️High-quality SiC wafer for Research and Experiment.
    ♦️Provide small quantities, special specifications products, and customized services.
    ♦️Global shipping, secure payment, large inventory.
    ♦️Minimum delivery time within 1 week. Shipped by FedEx, DHL,UPS, etc.
    SiC Substrate Specification:
    • Size: 2inch;
    • Poly tyep: 3C;
    • Diameter: 50mm±0.38;
    • Thickness: 350um±25;
    • Surface Orientation ,On axis:(111)0.5;
    • Micropipe Density: 0 cm-2;
    • Resistivity <0.8 m.cm;
    • Primary Flat Orientation : {1-10}±0.5°;
    • Primary Flat Length ：15.9mm1.7mm;
    • Secondary Flat Orientation : Silicon face up: 90CW. from Prime flat 5.0;
    • Secondary Flat Length : 8.0mm1.7 mm;
    • TTV≤5μm;
    • Warp≤15μm;
    • Bow≤-30μm;
    • Surface Roughness: CMPRa<0.2 nm;
    • Edge Cracks: 1 allowed,1 mm;
    • HexPlates: Cumulative areas3 %;
    • Polytype Areas : Cumulative areas5%;
    • Silicon Surface Scratches : 8 scratches to 1xwafer diametercumulative length;
    • Edge Chips : 5 allowed, 1mm each;
    • Silicon Surface Contamination : None;
    • Edge Exclusion : 3mm;
    • Surface finish: Double Side CMP;
    • Packing: Multi-wafer Cassette Or Single Wafer Container;
    • Production time: 4~5weeks;